1. Technical Field
The present invention relates to a semiconductor device and to a fabrication method thereof, and in particular to a semiconductor device with a high element-isolation breakdown voltage in impurity element-isolation regions, and to a fabrication method of the same.
2. Related Art
Along with developments in making electrical devices more compact and lowering their cost, there is also demand for more compactness in power transistors for installation in such electrical devices. In particular, technology for integrating a control circuit and plural power transistors (semiconductor elements) onto the same semiconductor substrate is essential in electrical devices that are subject to demands for even more compactness, such as mobile devices and household devices. When forming plural semiconductor elements on the same semiconductor substrate, methods exist for element-isolation between semiconductor elements by use of impurity element-isolation regions.
Apart from the above demands for more compactness and higher integration, there are also demands for higher breakdown voltages of semiconductor devices. Greater currents can be used for driving semiconductor devices accommodating such high breakdown voltages. Such semiconductor devices can prevent various current leaks and avoid latching up. For example, the breakdown voltage required in semiconductor devices is of the order of a few V for microcomputer, DRAM, and memory use, of the order of a few tens of V for LCD driver use, and of the order of several hundreds of V for high voltage display use.
An example of a high breakdown voltage electric field effect transistor (HVMOS: High Voltage Metal-Oxide-Semiconductor) will now be explained, with reference to FIG. 1.
As shown in FIG. 1, an HVMOS 200 is configured with a P-type silicon substrate 201, an N-type epitaxial layer 202 formed above the P-type silicon substrate 201, an N-type buried layer 203 selectively formed at the interface of the P-type silicon substrate 201 and the N-type epitaxial layer 202, an inter-layer insulating layer 204 formed above the N-type epitaxial layer 202, and a metal wiring layer 205 formed above the inter-layer insulating layer 204.
A P-type drift layer 206, a P-type high concentration region 207 (referred to below as P+ region), and a field oxide film 208 are formed on the N-type epitaxial layer 202. A gate oxidized film 209, and a gate electrode 210 that is made from poly-crystalline silicon, are formed above the N-type epitaxial layer 202. A P-type isolation region 211 electrically connected to the P-type silicon substrate 201 is formed in the N-type epitaxial layer 202. An element region of the HVMOS 200 is element-isolated by the P-type isolation region 211. The P+ region 207 is connected to the metal wiring layer 205 via a contact line 212 that penetrates through the inter-layer insulating layer 204.
The HVMOS 200 configured as described above can accommodate high breakdown voltages due to the N-type buried layer 203 formed at the interface of the P-type silicon substrate 201 and the N-type epitaxial layer 202. A reason for this is that the resistance value of the N-type region formed by the N-type epitaxial layer 202 and the N-type buried layer 203 is lower than the resistance value of the N-type epitaxial layer 202 alone, and so resistance to latch-up of the HVMOS 200 is raised. In addition, since isolation of the P-type silicon substrate 201 from the N-type epitaxial layer 202 is ensured by the N-type buried layer 203, leak current from the P-type silicon substrate 201 to the N-type epitaxial layer 202 is prevented from occurring, and robustness to noise can be raised.
In an HVMOS 200 such as that shown in FIG. 1, the isolation breakdown voltage between adjacent element regions is determined by the PN junction between the P-type isolation region 211 and the N-type epitaxial layer 202. If the isolation breakdown voltage between adjacent element regions is lower than the operating voltage of the HVMOS 200, then when the operating voltage is applied to a given metal line 205, a leak current occurs from the N-type epitaxial layer 202 of a semiconductor element that includes the metal wiring layer 205 to which the operating voltage has been applied, through the P-type isolation region 211, to the N-type epitaxial layer 202 of an adjacent semiconductor element. The HVMOS 200 can no longer be operated correctly when such a leak current occurs.
In Japanese Patent Application Laid-Open (JP-A) No. 5-299498 a semiconductor device is described that can achieve suppression of leak current and stronger latch-up resistance without the provision of a buried layer as described above. In the semiconductor device described in JP-A No. 5-299498, by provision of a channel stopper region in a silicon substrate bottom face, and by having a trench buried insulating film penetrating to the channel stopper region through the silicon substrate and through an impurity well region, suppression of leak current and stronger latch-up resistance can be achieved.
However, in the HVMOS 200 shown in FIG. 1, if an even higher breakdown voltage is required then there is the problem that sufficiently a high breakdown voltage cannot be achieved in practice.
The present invention is made in consideration of the above circumstances, and provides a semiconductor device with a buried layer formed at a semiconductor substrate and epitaxial layer interface, the semiconductor device enabling sufficiently higher breakdown voltage to be achieved. A fabrication method of the same is also provided.